Design considerations for PD/SOI SRAM: Impact of gate leakage and threshold voltage variation
- Rouwaida Kanj
- Rajiv V. Joshi
- et al.
- 2008
- IEEE Trans Semicond Manuf
Publications
4 results for Jayakumaran Sivagnaname
Gate leakage effects on yield and design considerations of PD/SOI SRAM designs
- Rouwaida Kanj
- Rajiv Joshi
- et al.
- 2007
- ISQED 2007
Wide limited switch dynamic logic circuit implementations
- Jayakumaran Sivagnaname
- Hung C. Ngo
- et al.
- 2006
- VLSID/Embedded 2006
Controlled-load limited switch dynamic logic circuit
- Jayakumaran Sivagnaname
- Hung C. Ngo
- et al.
- 2005
- ISQED 2005