Mobility scaling in short-channel length strained Ge-on-insulator P-MOSFETs
- Stephen W. Bedell
- Amlan Majumdar
- et al.
- 2008
- IEEE Electron Device Letters
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56 results for John Arnold
Plasma ash processing solutions for advanced interconnect technology
- N. Fuller
- M.A. Worsley
- et al.
- 2008
- Thin Solid Films
Band-edge high-performance high-κ /metal gate n-MOSFETs using cap layers containing group IIA and IIIB elements with gate-first processing for 45 nm and beyond
- V. Narayanan
- V.K. Paruchuri
- et al.
- 2006
- VLSI Technology 2006
Process optimization for high electron mobility in nMOSFETs with aggressively scaled HfO2/metal stacks
- V. Narayanan
- K. Maitra
- et al.
- 2006
- IEEE Electron Device Letters
Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing
- H.S. Yang
- R. Malik
- et al.
- 2004
- IEDM 2004
Simulation of surface topography evolution during plasma etching by the method of characteristics
- Manoj Dalvie
- Satoshi Hamaguchi
- 1994
- Journal of Vacuum Science and Technology A: Vacuum, Surfaces and Films