High performance 45-nm SOI technology with enhanced strain, porous low-k BEOL, and immersion lithography
- S. Narasimha
- K. Onishi
- et al.
- 2006
- IEDM 2006
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8 results for Robert Wong
Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing
- H.S. Yang
- R. Malik
- et al.
- 2004
- IEDM 2004
Incorporating process variation contours in design rule calculation and SRAM design optimization
- Dongbing Shao
- Jing Sha
- et al.
- 2019
- SPIE Advanced Lithography 2019
Layout based Monte-Carlo simulation (LBMCS) for complex back end of line (BEOL) design rule study
- Dongbing Shao
- Lawrence Clevenger
- et al.
- 2017
- IITC 2017
Product burn-in stress impacts on SRAM array performance
- Li Wang
- Qiuyi Ye
- et al.
- 2007
- IRPS 2007
Impact of NBTI induced statistical variation to SRAM cell stability
- Giuseppe La Rosa
- Wee Loon Ng
- et al.
- 2006
- IRPS 2006
SRAM Cell Design for Stability Methodology
- Clement Wann
- Robert Wong
- et al.
- 2005
- VLSI Technology 2005
Super fast physics-based methodology for accurate memory yield prediction
- Rajiv V. Joshi
- Keunwoo Kim
- et al.
- 2015
- IEEE Transactions on VLSI Systems