Custom Sub-Systems and Circuits for Deep Learning: Guest Editorial Overview
- Chia-Yu Chen
- Boris Murmann
- et al.
- 2019
- IEEE JESTCS
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A low-noise folded bit-line sensing architecture for multigigabit DRAM with ultrahigh-density 6F2 cell
- Jong-Shik Kim
- Yu-Soo Choi
- et al.
- 1998
- IEEE Journal of Solid-State Circuits