New Optimal Design Strategies and Analysis of Ultra-Low Leakage Circuits for Nano-Scale SOI Technology
- Koushik K. Das
- Rajiv V. Joshi
- et al.
- 2003
- ISLPED 2003
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199 results for Rajiv V. Joshi
Strained-Si Devices and Circuits for Low-Power Applications
- Keunwoo Kim
- Rajiv V. Joshi
- et al.
- 2003
- ISLPED 2003
Design considerations of scaled sub-0.1 μm PD/SOI CMOS circuits
- C.T. Chuang
- R.V. Joshi
- et al.
- 2003
- ISQED 2003
Performance assessment of scaled strained-Si channel-on-insulator (SSOI) CMOS
- Keunwoo Kim
- Ching-Te Chuang
- et al.
- 2002
- IEEE International SOI Conference 2002
High performance SRAMs in 1.5 V, 0.18μm partially depleted SOI technology
- R.V. Joshi
- A. Pellela
- et al.
- 2002
- VLSI Circuits 2002
SOI-optimized 64-bit high-speed CMOS adder design
- Jae-Joon Kim
- Rajiv Joshi
- et al.
- 2002
- VLSI Circuits 2002
Thermal conductivity model for thin silicon-on-insulator layers at high temperatures
- Mehdi Asheghi
- Bahareh Behkam
- et al.
- 2002
- IEEE International SOI Conference 2002
High performance low power VT- wave-pipeline CMOS circuit in PD/SOI technology
- R.V. Joshi
- F. Yee
- et al.
- 2002
- IEEE International SOI Conference 2002
Analysis of the effect of the gate oxide breakdown on SRAM stability
- R. Rodríguez
- J.H. Stathis
- et al.
- 2002
- Microelectronics Reliability
High performance SOI/Cu SRAMs and memories in microprocessors
- R.V. Joshi
- S.S. Kang
- et al.
- 2001
- AMC 2001