Novel circuits to improve SRAM performance in PD/SOI technology
- R.V. Joshi
- A.J. Bhavnagarwala
- et al.
- 2001
- IEEE International SOI Conference 2001
Publications
Date
Featured collections
Popular topics
199 results for Rajiv V. Joshi
Mixed multi-threshold differential cascode voltage switch (MT-DCVS) circuit styles and strategies for low power VLSI design
- W. Chen
- W. Hwang
- et al.
- 2001
- ISLPED 2001
Effects of gate-to-body tunneling current on PD/SOI CMOS SRAM
- R.V. Joshi
- C.T. Chuang
- et al.
- 2001
- VLSI Technology 2001
SOI for asynchronous dynamic circuits
- R.V. Joshi
- W. Hwang
- et al.
- 2001
- GLSVLSI 2001
Design of provably correct storage arrays
- R.V. Joshi
- W. Hwang
- et al.
- 2001
- VLSID 2001
`Cool low power' 1 GHz multi-port register file and dynamic latch in 1.8 V, 0.25 μm SOI and bulk technology
- R.V. Joshi
- W. Hwang
- et al.
- 2000
- ISLPED 2000
High frequency input isolation circuit for asynchronous CMOS macros in PD/SOI technology
- R.V. Joshi
- W. Hwang
- et al.
- 2000
- IEEE International SOI Conference 2000
`Cool low power' 1 GHz multi-port register file and dynamic latch in 1.8 V, 0.25 μm SOI and bulk technology
- R.V. Joshi
- W. Hwang
- et al.
- 2000
- ISLPED 2000
2 GHz cycle, 430 ps access time 34 Kb L1 directory SRAM in 1.5 V, 0.18 μm CMOS bulk technology
- R.V. Joshi
- S.P. Kowalczyk
- et al.
- 2000
- VLSI Circuits 2000
Frequency dependent behavior of a high performance dynamic register file in 1.8 V, 0.25 μm SOI technology
- R.V. Joshi
- W. Hwang
- et al.
- 1999
- IEEE International SOI Conference 1999