Design considerations and implementations of a high performance dynamic register file
- R.V. Joshi
- W. Hwang
- 1999
- VLSID 1999
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199 results for Rajiv V. Joshi
Designing a testable System on a Chip
- S.V. Kosonocky
- A.A. Bright
- et al.
- 1998
- VTS 1998
660 MHz self-resetting 8 port, 32×64 bits register file and latch in 0.25 μm SOI technology
- R.V. Joshi
- W. Hwang
- et al.
- 1998
- IEEE International SOI Conference 1998
Pulse-to-static conversion latch with a self-timed control circuit
- W. Hwang
- R.V. Joshi
- et al.
- 1997
- ICCD 1997
Development of a high bandwidth merged logic/DRAM multimedia chip
- W.K. Luk
- Y. Katayama
- et al.
- 1997
- ICCD 1997
500 MHz 32-word×64-bit 8-port self-resetting CMOS register file and associated dynamic-to-static latch
- W.H. Henkels
- W. Hwang
- et al.
- 1997
- VLSI Circuits 1997
A novel application of polyimide-W-AI/CU for VLSI interconnect
- R.V. Joshi
- L. Hsu
- et al.
- 1991
- VMIC 1991
Low-resistance submicron CVD W interlevel via plugs on Al-Cu-Si
- R.V. Joshi
- S.B. Brodsky
- et al.
- 1989
- VMIC 1989
LPCVD TUNGSTEN SILICIDE WITH TITANIUM UNDERLAYER.
- R.V. Joshi
- L. Krusin-Elbaum
- et al.
- 1985
- VLSI Technology 1985
An Energy-Efficient Digital ReRAM-Crossbar-Based CNN With Bitwise Parallelism
- Leibin Ni
- Zichuan Liu
- et al.
- 2017
- IEEE JXCDC