A Disturb Decoupled Column Select 8T SRAM Cell
- Vinod Ramadurai
- Rajiv Joshi
- et al.
- 2007
- CICC 2007
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199 results for Rajiv V. Joshi
Gate leakage effects on yield and design considerations of PD/SOI SRAM designs
- Rouwaida Kanj
- Rajiv Joshi
- et al.
- 2007
- ISQED 2007
The design and implementation of a low-overhead supply-gated SRAM
- J.B. Kuang
- Hung Ngo
- et al.
- 2006
- ESSCIRC 2006
A low power and high performance SOI SRAM circuit design with improved cell stability
- R.V. Joshi
- Y. Chan
- et al.
- 2006
- IEEE SOI 2006
Statistical exploration of the dual supply voltage space of a 65nm PD/SOI CMOS SRAM cell
- Rajiv Joshi
- Rouwaida Kanj
- et al.
- 2006
- ESSDERC 2006
Technology impacts on sub-90nm CMOS circuit design & design methodologies
- Ruchir Puri
- Tanay Karnik
- et al.
- 2006
- VLSID 2006
Modeling and analysis of gate leakage in ultra-thin oxide sub-50nm double gate devices and circuits
- Saibal Mukhopadhyay
- Keunwoo Kim
- et al.
- 2005
- ISQED 2005
3-D thermal modeling of FinFET
- R.V. Joshi
- José A. Pascual-Gutiérrez
- et al.
- 2005
- ESSDERC 2005
A novel circuit topology for generating and validating digitally sense amplifier differentials for bulk and SOI
- Rajiv V. Joshi
- Yuen Chan
- 2005
- ESSCIRC 2005
Direct temperature measurement for VLSI circuits and 3-D modeling of self-heating in sub-0.13 μm SOI technologies
- R.V. Joshi
- S.S. Kang
- et al.
- 2005
- VLSID 2005