A new planarization technique, using a combination of RIE and chemical mechanical polish (CMP)
- B. Davari
- C. Koburger
- et al.
- 1989
- IEDM 1989
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131 results for J. Warnock
23 ps/2.1 mW ECL gate
- Kai-Yap Toh
- C.T. Chuang
- et al.
- 1989
- ISSCC 1989
Variable-size shallow trench isolation (STI) technology with diffused sidewall doping for submicron CMOS
- B. Davari
- C. Koburger
- et al.
- 1988
- IEDM 1988
Sub-50 ps single poly planar bipolar technology
- T.C. Chen
- D.D. Tang
- et al.
- 1988
- IEDM 1988
The 12-core POWER8™ processor with 7.6 Tb/s IO bandwidth, integrated voltage regulation, and resonant clocking
- Eric J. Fluhr
- Steve Baumgartner
- et al.
- 2015
- IEEE JSSC
High-Performance Devices for a 0.15-μm CMOS Technology
- G. Shahidi
- James Warnock
- et al.
- 1993
- IEEE Electron Device Letters
A Scaled 0.25- μm Bipolar Technology Using Full e-Beam Lithography
- John D. Cressler
- James Warnock
- et al.
- 1992
- IEEE Electron Device Letters
BiCMOS Technology with 60-GHz n-p-n Bipolar and 0.25-μm CMOS
- James Warnock
- Ghavam G. Shahidi
- et al.
- 1992
- IEEE Electron Device Letters
Spin superlattice behavior in ZnSe/Zn0.99Fe0.01Se quantum wells
- W.C. Chou
- A. Petrou
- et al.
- 1991
- Physical Review Letters
High-Performance Bipolar Technology for Improved ECL Power Delay
- J. Warnock
- J.D. Cressler
- et al.
- 1991
- IEEE Electron Device Letters