Circuit and PD challenges at the 14nm technology node
- James Warnock
- 2013
- ISPD 2013
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131 results for J. Warnock
An elegant hardware-corroborated statistical repair and test methodology for conquering aging effects
- Rouwaida Kanj
- Rajiv Joshi
- et al.
- 2009
- ICCAD 2009
Key features of the design methodology enabling a multi-core SoC implementation of a first-generation CELL processor
- Dac Pham
- Hans-Werner Anderson
- et al.
- 2006
- ASP-DAC 2006
The design methodology and implementation of a first-generation CELL processor: A multi-core SoC
- D.C. Pham
- E. Behnen
- et al.
- 2005
- CICC 2005
The design and implementation of a first-generation CELL processor - A multi-core SoC
- D.C. Pham
- S. Asano
- et al.
- 2005
- ICICDT 2005
The design and implementation of double-precision multiplier in a first-generation CELL processor
- J.B. Kuang
- T.C. Buchholtz
- et al.
- 2005
- ICICDT 2005
Circuit design issues for the POWER4 chip
- J. Warnock
- 2003
- VLSI-TSA 2003
High performance CMOS circuit techniques for the G-4 S/390 microprocessor
- J. Warnock
- L. Sigal
- et al.
- 1997
- ICCD 1997
Fully-scaled 0.25-micron bipolar technology using variable shaped electron-beam lithography
- Philip J. Coane
- Kaolin G. Chiong
- et al.
- 1993
- Microlithography 1993
A room temperature 0.1 μm CMOS on SOI
- G. Shahidi
- C. Blair
- et al.
- 1993
- VLSI Technology 1993