BEOL process integration for the 7 nm technology node
- T. Standaert
- Genevieve Beique
- et al.
- 2016
- IITC/AMC 2016
Publications
Date
Featured collections
Popular topics
19 results for Joe Lee
Post porosity plasma protection integration at 48 nm pitch
- H. Huang
- Krystelle Lionti
- et al.
- 2016
- IITC/AMC 2016
Electrical properties and reliability of ALD TaN barrier for sub-90nmPitch Cu interconnects
- Tibor Bolom
- J. Lee
- et al.
- 2013
- ADMETA 2013
Electromigration comparison of selective CVD cobalt capping with PVD Ta(N) and CVD cobalt liners on 22nm-groundrule dual-damascene Cu interconnects
- A. Simon
- Tibor Bolom
- et al.
- 2013
- IRPS 2013
Electrical and reliability evaluation of Cu/Low-k integration: Exploration of PVD barrier/seed and CVD SiC(N,H) cap depositions
- C.-C. Yang
- D. Edelstein
- et al.
- 2004
- ADMETA 2004
Reliability, yield, and performance of a 90 nm SOI/Cu/SiCOH technology
- D. Edelstein
- C.R. Davis
- et al.
- 2004
- IITC 2004
Comprehensive reliability evaluation of a 90 nm CMOS technology with Cu/PECVD low-k BEOL
- D. Edelstein
- H.S. Rathore
- et al.
- 2004
- IRPS 2004
Comprehensive reliability evaluation of a 90 nm CMOS technology with Cu/PECVD low-k BEOL
- D. Edelstein
- H.S. Rathore
- et al.
- 2004
- IRPS 2004
Self-aligned blocking integration demonstration for critical sub-30-nm pitch Mx level patterning with EUV self-aligned double patterning
- Angelique Raley
- Joe Lee
- et al.
- 2019
- J. Micro/Nanolithogr. MEMS MOEMS