Hardware-assisted 3D TCAD for predictive capacitance extraction in 32nm SOI SRAMs
- Ajay N. Bhoj
- Rajiv Joshi
- et al.
- 2011
- IEDM 2011
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8 results for Sudesh Saroop
A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications
- S. Krishnan
- U. Kwon
- et al.
- 2011
- IEDM 2011
A 32nm 0.5V-supply dual-read 6T SRAM
- Jente B. Kuang
- J. Schaub
- et al.
- 2010
- CICC 2010
High performance 32nm SOI CMOS with high-k/metal gate and 0.149μm 2 SRAM and ultra low-k back end with eleven levels of copper
- B. Greene
- Q. Liang
- et al.
- 2009
- VLSI Technology 2009
A universal hardware-driven PVT and layout-aware predictive failure analytics for SRAM
- Rajiv V. Joshi
- Sudesh Saroop
- et al.
- 2016
- IEEE Transactions on VLSI Systems
Super fast physics-based methodology for accurate memory yield prediction
- Rajiv V. Joshi
- Keunwoo Kim
- et al.
- 2015
- IEEE Transactions on VLSI Systems
Novel 4 GHz interleaved SRAM cells with asymmetrical precharge in 45 nm PDSOI technology
- Rajiv V. Joshi
- Rouwaida Kanj
- et al.
- 2014
- IEEE Trans Semicond Manuf
The design and characterization of a half-volt 32 nm dual-read 6T SRAM
- Jente B. Kuang
- Jeremy D. Schaub
- et al.
- 2011
- IEEE TCAS-I