A 45 nm CMOS node Cu/low-k/ ULtra low-k PECVD SiCOH (k=2.4) BEOL technology
- S. Sankaran
- S. Arai
- et al.
- 2006
- IEDM 2006
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9 results for Chunyan Tian
High performance 45-nm SOI technology with enhanced strain, porous low-k BEOL, and immersion lithography
- S. Narasimha
- K. Onishi
- et al.
- 2006
- IEDM 2006
Process dependence of AC/DC PBTI in HKMG n-MOSFETs
- Wen Liu
- Giuseppe La Rosa
- et al.
- 2014
- IRPS 2014
Intrinsic dielectric stack reliability of a high performance bulk planar 20nm replacement gate high-k metal gate technology and comparison to 28nm gate first high-k metal gate process
- W. McMahon
- C. Tian
- et al.
- 2013
- IRPS 2013
High performance bulk planar 20nm CMOS technology for low power mobile applications
- Huiling Shang
- Sameer Jain
- et al.
- 2012
- VLSI Technology 2012
High performance transistors featured in an aggressively scaled 45nm bulk CMOS technology
- Z. Luo
- N. Rovedo
- et al.
- 2007
- VLSI Technology 2007
Reliability investigation of NiPtSi electrical fuse with different programming mechanisms
- C. Tian
- D. Moy
- et al.
- 2007
- IIRW 2007
Reliability qualification of CoSI2 electrical fuse for 90NM technology
- C. Tian
- B. Park
- et al.
- 2006
- IRPS 2006
Breakdown data generation and in-die deconvolution methodology to address BEOL and MOL dielectric breakdown challenges
- F. Chen
- Carole Graas
- et al.
- 2015
- Microelectronics Reliability