Deterministic Frequency and Voltage Enhancements on the POWER10 ProcessorBrian VanderpoolPhillip J. Restleet al.2023IEEE JSSC
Design Considerations for Reconfigurable Delay Circuit to Emulate System Critical PathsXiaobin YuanPawel Owczarczyket al.2015IEEE Transactions on VLSI Systems
Single-cycle, pulse-shaped critical path monitor in the POWER7+ microprocessorAlan J. DrakeMichael S. Floydet al.2013ISLPED 2013