Oxygen vacancy traps in Hi-K/Metal gate technologies and their potential for embedded memory applications
- C. Kothandaraman
- X. Chen
- et al.
- 2015
- IRPS 2015
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7 results for D. Ioannou
Impact of 3D copper TSV integration on 32SOI FEOL and BEOL reliability
- Mukta Farooq
- Giuseppe La Rosa
- et al.
- 2015
- IRPS 2015
Pulsed gate dielectric breakdown in a 32 nm technology under different ESD stress configurations
- Yang Yang
- Robert Gauthier
- et al.
- 2010
- EOS/ESD 2010
Characterization of high-k/metal gate stack breakdown in the time scale of ESD events
- Yang Yang
- James Di Sarro
- et al.
- 2010
- IRPS 2010
ESD time-domain characterization of high-k gate dielectric in a 32 nm CMOS technology
- James Di Sarro
- Yang Yang
- et al.
- 2009
- EOS/ESD 2009
Electrostatic discharge induced oxide breakdown characterization in a 0.1 μm CMOS technology
- A. Salman
- R. Gauthier
- et al.
- 2002
- IRPS 2002
Degradation of high-κ/metal gate nMOSFETs under ESD-like stress in a 32-nm technology
- Yang Yang
- Robert J. Gauthier
- et al.
- 2011
- IEEE T-DMR