Optimal UTB FD/SOI device structure using thin BOX for sub-50-nm SRAM design
- Saibal Mukhopadhyay
- Keunwoo Kim
- et al.
- 2006
- IEEE Electron Device Letters
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33 results for X. Wang
High-κ gate dielectrics for nanoscale CMOS devices: Status, challenges, and future
- Dae-Gyu Park
- Xinlin Wang
- 2010
- ECS Transactions
FinFET resistance mitigation through design and process optimization
- Cindy Wang
- Josephine Chang
- et al.
- 2009
- VLSI-TSA 2009
Low-k spacers for advanced low power CMOS devices with reduced parasitic capacitances
- Elbert Huang
- Eric Joseph
- et al.
- 2008
- IEEE International SOI Conference 2008
Device scaling of high performance MOSFET with metal gate high-K at 32nm technology node and beyond
- Xinlin Wang
- Ghavam Shahidi
- et al.
- 2008
- SISPAD 2008
FinFET performance advantage at 22nm: An AC perspective
- M. Guillorn
- J. Chang
- et al.
- 2008
- VLSI Technology 2008
A cost effective 32nm high-K/metal gate CMOS technology for low power applications with single-metal/gate-first process
- X. Chen
- S. Samavedam
- et al.
- 2008
- VLSI Technology 2008
High-performance high-κ/metal gates for 45nm CMOS and beyond with gate-first processing
- M. Chudzik
- B. Doris
- et al.
- 2007
- VLSI Technology 2007
Simulation study of multiple FIN FinFET design for 32nm technology node and beyond
- Xinlin Wang
- Andres Bryant
- et al.
- 2007
- SISPAD 2007
Poly-Si/AlN/HfSiO stack for ideal threshold voltage and mobility in sub-100 nm MOSFETs
- K.-L. Lee
- M.M. Frank
- et al.
- 2006
- VLSI Technology 2006