Gate-dielectric permitivity and metal-gate work-function tradeoff in Lmet = 25 nm PDSOI device characteristics
- Dechao Guo
- Andres Bryant
- et al.
- 2006
- IEEE Electron Device Letters
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33 results for X. Wang
Optimal UTB FD/SOI device structure using thin BOX for sub-50-nm SRAM design
- Saibal Mukhopadhyay
- Keunwoo Kim
- et al.
- 2006
- IEEE Electron Device Letters
Optimization of high κ gate stacks with poly-Si, FUSI and metal electrodes
- R. Jammy
- V. Narayanan
- et al.
- 2005
- ISTC 2005
Simulation analysis of series resistance for SOI MOSFET in nanometer regime
- Xinlin Wang
- Phil Oldiges
- et al.
- 2005
- SISPAD 2005
Dual stress liner enhancement in hybrid orientation technology
- C. Sheraw
- M. Yang
- et al.
- 2005
- VLSI Technology 2005
Poly-Si/high-k gate stacks with near-ideal threshold voltage and mobility
- M.M. Frank
- V.K. Paruchuri
- et al.
- 2005
- VLSI-TSA 2005
Performance comparison and channel length scaling of strained Si FETs on SiGe-on-insulator (SGOI)
- J. Cai
- K. Rim
- et al.
- 2004
- IEDM 2004
Fabrication, device design and mobility enhancement of germanium channel MOSFETs
- Huiling Shang
- E. Gousev
- et al.
- 2004
- ICSICT 2004
Channel design and mobility enhancement in strained germanium buried channel MOSFETs
- H. Shang
- J.O. Chu
- et al.
- 2004
- VLSI Technology 2004
Electrostatic analysis of carbon nanotube arrays
- Xinlin Wang
- H.-S. Wong
- et al.
- 2003
- SISPAD 2003