A novel, low-cost deep trench decoupling capacitor for high-performance, low-power bulk CMOS applications
- Chengwen Pei
- Roger Booth
- et al.
- 2008
- ICSICT 2008
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17 results for P. Parries
Analysis of retention time distribution of embedded DRAM - A new mMethod to characterize across-chip threshold voltage variation
- W. Kong
- P. Parries
- et al.
- 2008
- IEEE ITC 2008
Access transistor design and optimization for 65/45nm high performance SOI eDRAM
- G. Wang
- P. Parries
- et al.
- 2008
- VLSI-TSA 2008
A one MB cache subsystem prototype with 2GHz embedded DRAMs in 45nm SOI CMOS
- Peter Klim
- John Barth
- et al.
- 2008
- VLSI Circuits 2008
A 0.168μm 2/0.11μm 2 highly scalable high performance embedded DRAM cell for 90/65-nm logic applications
- G. Wang
- P. Parries
- et al.
- 2005
- VLSI Technology 2005
A 1 MB cache subsystem prototype with 1.8 ns embedded DRAMs in 45 nm SOI CMOS
- Peter J. Klim
- John Barth
- et al.
- 2009
- IEEE Journal of Solid-State Circuits
A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier
- John Barth
- William R. Reohr
- et al.
- 2008
- IEEE Journal of Solid-State Circuits