A 64Gb/s 1.4pJ/b NRZ optical-receiver data-path in 14nm CMOS FinFET
- Alessandro Cevrero
- Ilter Ozkaya
- et al.
- 2017
- ISSCC 2017
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87 results for Pier Andrea Francese
A 30Gb/s 0.8pJ/b 14nm FinFET receiver data-path
- 2016
- ISSCC 2016
A feedforward controlled on-chip switched-capacitor voltage regulator delivering 10W in 32nm SOI CMOS
- Toke M. Andersen
- Florian Krismer
- et al.
- 2015
- ISSCC 2015
A 90GS/s 8b 667mW 64× interleaved SAR ADC in 32nm digital SOI CMOS
- Lukas Kull
- Thomas Toifl
- et al.
- 2014
- ISSCC 2014
A sub-ns response on-chip switched-capacitor DC-DC voltage regulator delivering 3.7W/mm2 at 90% efficiency using deep-trench capacitors in 32nm SOI CMOS
- Toke Meyer Andersen
- Florian Krismer
- et al.
- 2014
- ISSCC 2014
A 3.1mW 8b 1.2GS/s single-channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32nm digital SOI CMOS
- Lukas Kull
- Thomas Toifl
- et al.
- 2013
- ISSCC 2013
HERMES-Core-A 1.59-TOPS/mm2PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs
- Riduan Khaddam-Aljameh
- Milos Stanisavljevic
- et al.
- 2022
- IEEE JSSC
A 64-core mixed-signal in-memory compute chip based on phase-change memory for deep neural network inference
- Manuel Le Gallo
- Riduan Khaddam-Aljameh
- et al.
- 2023
- Nature Electronics
A 72-GS/s, 8-Bit DAC-Based Wireline Transmitter in 4-nm FinFET CMOS for 200+ Gb/s Serial Links
- Timothy O. Dickson
- Zeynep Toprak Deniz
- et al.
- 2023
- IEEE JSSC
Efficient Pipelined Execution of CNNs Based on In-Memory Computing and Graph Homomorphism Verification
- Martino Dazzi
- Abu Sebastian
- et al.
- 2021
- IEEE TC