An SRAM-Based Multibit In-Memory Matrix-Vector Multiplier with a Precision That Scales Linearly in Area, Time, and Power
- Riduan Khaddam-Aljameh
- Pier Andrea Francese
- et al.
- 2021
- IEEE Transactions on VLSI Systems
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87 results for Pier Andrea Francese
A Discrete Multitone Wireline Transceiver Datapath With On-Chip Sign-Sign LMS Adaptation And Loading Profile Optimization On RFSoC
- Jaewon Lee
- Seoyoung Jang
- et al.
- 2024
- IEEE TCAS-II
A 2-Lane Discrete Multitone Wireline Receiver Datapath With Far-End Crosstalk Cancellation On RFSoC Platform
- Jaewon Lee
- Seoyoung Jang
- et al.
- 2024
- IEEE TCAS-II
A DAC/ADC-based Wireline Transceiver Datapath Functional Verification on RFSoC Platform
- Jaewon Lee
- Seoyoung Jang
- et al.
- 2024
- IEEE TCAS-II
Design of synchronous frequency dividers in 5-nm FinFET CMOS technology
- 2023
- Electronics Letters
Design of Time-Encoded Spiking Neural Networks in 7-nm CMOS Technology
- Sandro Widmer
- Marcel Kossel
- et al.
- 2023
- IEEE TCAS-II
An 8b 1.0-to-1.25 GS/s Time-Based ADC With Bipolar VTC and Sense Amplifier Latch Interpolated Gated Ring Oscillator TDC
- A. Serdar Yonar
- Pier Andrea Francese
- et al.
- 2023
- IEEE SSC-L
An In-Comparator Aperture-Time Equalization in a 7-nm FinFET CMOS 40-Gb/s Receiver
- Abdullah Serdar Yonar
- Pier Andrea Francese
- et al.
- 2020
- IEEE SSC-L
Deep learning acceleration based on in-memory computing
- Evangelos Eleftheriou
- Geethan Karunaratne
- et al.
- 2019
- IBM J. Res. Dev
BBPD with wide input phase range
- Marcel Kossel
- Pier Andrea Francese
- et al.
- 2019
- Electronics Letters