A 3.1mW/Gbps 30Gbps quarter-rate triple-speculation 15-tap SC-DFE RX data path in 32nm CMOS
- Thomas Toifl
- Michael Ruegg
- et al.
- 2012
- VLSI Circuits 2012
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100 results for Marcel Kossel
A 2.6mW/Gbps 12.5Gbps RX with 8-tap switched-cap DFE in 32nm CMOS
- Thomas Toifl
- Christian Menolfi
- et al.
- 2011
- VLSI Circuits 2011
Design and phase noise analysis of a multiphase 6 to 11 GHz PLL
- George Von Bueren
- David Barras
- et al.
- 2009
- ESSCIRC 2009
A small-area voltage regulator with high-bandwidth supply-rejection using a regulated replica in 45nm CMOS SOI
- Thomas Toifl
- Christian Menolfi
- et al.
- 2008
- A-SSCC 2008
A low-power 40 Gbit/s receiver circuit based on full-swing CMOS-style clocking
- Thomas Toifl
- Christian Menolfi
- et al.
- 2007
- CSICS 2007
A 40 Gb/s optical receiver in 80-nm CMOS for short-distance high-density interconnects
- C. Kromer
- G. Sialm
- et al.
- 2006
- A-SSCC 2006
Electrical and optical transceivers for short-range data communication, fabricated in VLSI 90-nm bulk and SOI CMOS technology
- Thomas Morf
- Christian Menolfi
- et al.
- 2005
- CSICS 2005
A 22 Gbit/s PAM-4 receiver in 90nm CMOS-SOI technology
- Thomas Toifl
- Christian Menolfi
- et al.
- 2005
- VLSI Circuits 2005
A multiphase PLL for 10 Gb/s links in SOI CMOS technology
- Marcel Kossel
- Thomas Morf
- et al.
- 2004
- RFIC 2004
Design and implementation of an optical interconnect demonstrator with board-integrated waveguides and microlens coupling
- Christoph Berger
- Urs Bapst
- et al.
- 2004
- IEE/LEOS Summer Topical Meetings 2004