Sub-30 nm pitch line-space patterning of semiconductor and dielectric materials using directed self-assembly
- Hsin-Yu Tsai
- Hiroyuki Miyazoe
- et al.
- 2012
- Journal of Vacuum Science and Technology B:Nanotechnology and Microelectronics
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65 results for Michael Guillorn
Pattern collapse mitigation strategies for EUV Lithography
- Dario L. Goldfarb
- Robert L. Bruce
- et al.
- 2012
- SPIE Advanced Lithography 2012
Scaling of SOI FinFETs down to fin width of 4 nm for the 10nm technology node
- Josephine Chang
- Michael A. Guillorn
- et al.
- 2011
- VLSI Technology 2011
A 0.021 μm2 trigate SRAM cell with aggressively scaled gate and contact pitch
- Michael A. Guillorn
- Josephine Chang
- et al.
- 2011
- VLSI Technology 2011
Understanding short-term BTI behavior through comprehensive observation of gate-voltage dependence of RTN in highly scaled high-κ / metal-gate pFETs
- Hiroshi Miki
- M. Yamaoka
- et al.
- 2011
- VLSI Technology 2011
Modeling of width-quantization-induced variations in logic FinFETs for 22nm and beyond
- Chung-Hsun Lin
- Wilfried Haensch
- et al.
- 2011
- VLSI Technology 2011
Impact of HK / MG stacks and future device scaling on RTN
- Naoki Tega
- Hiroshi Miki
- et al.
- 2011
- IRPS 2011
Systematic studies on reactive ion etch-induced deformations of organic underlayers
- Martin Glodde
- Sebastian Engelmann
- et al.
- 2011
- SPIE Advanced Lithography 2011
Non-planar device architecture for 15nm node: FinFET or trigate?
- Chung-Hsun Lin
- Josephine Chang
- et al.
- 2010
- IEEE International SOI Conference 2010
Hysteretic drain-current behavior due to random telegraph noise in scaled-down FETs with high-κ/metal-gate stacks
- Hiroshi Miki
- Naoki Tega
- et al.
- 2010
- IEDM 2010