An integral path self-calibration scheme for a dual-loop PLL
- Mark Ferriss
- Jean-Olivier Plouchart
- et al.
- 2013
- IEEE JSSC
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69 results for Daniel Friedman
A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology
- John F. Bulzacchelli
- Christian Menolfi
- et al.
- 2012
- IEEE JSSC
Cryogenic CMOS: design considerations for future quantum computing systems
- Rajiv V. Joshi
- J.O. Plouchart
- et al.
- 2023
- CICC 2023
A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology
- Timothy O. Dickson
- Yong Liu
- et al.
- 2014
- CICC 2014
A 60GHz, linear, direct down-conversion mixer with mm-Wave tunability in 32nm CMOS SOI
- Mihai Sanduleanu
- Alberto Valdes-Garcia
- et al.
- 2013
- CICC 2013
Indirect performance sensing for on-chip analog self-healing via Bayesian model fusion
- S. Sun
- F. Wang
- et al.
- 2013
- CICC 2013
A 28GHz hybrid PLL in 32nm SOI CMOS
- Mark Ferriss
- Alexander Rylyakov
- et al.
- 2013
- VLSI Circuits 2013
A linearized voltage-controlled oscillator for dual-path phase-locked loops
- Glenn E. R. Cowan
- Mounir Meghelli
- et al.
- 2013
- ISCAS 2013
A 3.2GS/s 4.55b ENOB two-step subranging ADC in 45nm SOI CMOS
- Jean-Olivier Plouchart
- Mihai Sanduleanu
- et al.
- 2012
- CICC 2012
A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS
- Jean-Olivier Plouchart
- Mark A. Ferriss
- et al.
- 2012
- CICC 2012