An alternative low resistance MOL technology with electroplated rhodium as contact plugs for 32nm CMOS and beyond
- I. Shao
- J.M. Cotte
- et al.
- 2007
- IITC 2007
Publications
Date
Featured collections
Popular topics
28 results for A. Topol
Improved manufacturability of Cu bond pads and implementation of seal design in 3D integrated circuits and packages
- K.N. Chen
- C. Tsang
- et al.
- 2006
- VMIC 2006
Lower resistance scaled metal contacts to silicide for advanced CMOS
- A. Topol
- C. Sheraw
- et al.
- 2006
- VLSI Technology 2006
Novel approach to reduce source/drain series resistance in high performance CMOS devices using self-aligned CoWP process for 45nm node UTSOI transistors with 20nm gate length
- James Pan
- Anna Topol
- et al.
- 2006
- VLSI Technology 2006
3D integrated circuits and silicon carrier packaging realization
- Cornelia K. Tsang
- Anna W. Topol
- 2006
- VMIC 2006
Critical aspects of layer transfer and alignment tolerances for 3D integration processes
- D.C. La Tulipe
- L.T. Shi
- et al.
- 2006
- GBC 2006
Stable SRAM cell design for the 32 nm node and beyond
- Leland Chang
- David M. Fried
- et al.
- 2005
- VLSI Technology 2005
High performance FDSOI CMOS technology with metal gate and high-k
- Bruce Doris
- Y.-H. Kim
- et al.
- 2005
- VLSI Technology 2005
Mobility and CMOS devices/circuits on sub-10nm (110) ultra thin body SOI
- Huiling Shang
- J. Rubino
- et al.
- 2005
- VLSI Technology 2005
Assembly technology for three dimensional integrated circuits
- A. Topol
- D.C. La Tulipe
- et al.
- 2005
- VMIC 2005