Gate stack resistance and limits to CMOS logic performance
- Richard A. Wachnik
- S. Lee
- et al.
- 2013
- CICC 2013
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3 results for Raphael Bingert
A novel low resistance gate fill for extreme gate length scaling at 20nm and beyond for gate-last high-k/metal gate CMOS technology
- U. Kwon
- K. Wong
- et al.
- 2012
- VLSI Technology 2012
Gate stack resistance and limits to CMOS logic performance
- Richard A. Wachnik
- Sungjae Lee
- et al.
- 2014
- IEEE TCAS-I