Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing
- H.S. Yang
- R. Malik
- et al.
- 2004
- IEDM 2004
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10 results for W.L. Lai
Critical Assessment of Soft Breakdown Stability Time and the Implementation of New Post-Breakdown Methodology for ultra-thin gate oxides
- E. Wu
- J. Suñé
- et al.
- 2003
- IEDM 2003
A high performance 90 nm SOI technology with 0.992 μm2 6T-SRAM cell
- Mukesh Khare
- S. Ku
- et al.
- 2002
- IEDM 2002
The effect of change of voltage acceleration on temperature activation of oxide breakdown for ultrathin oxides
- E. Wu
- J.M. McKenna
- et al.
- 2001
- IEEE Electron Device Letters
Simple Gate Metal Anneal (SIGMA) stack for FinFET Replacement Metal Gate toward 14nm and beyond
- Takashi Ando
- B. Kannan
- et al.
- 2014
- VLSI Technology 2014
Process dependence of AC/DC PBTI in HKMG n-MOSFETs
- Wen Liu
- Giuseppe La Rosa
- et al.
- 2014
- IRPS 2014
Intrinsic dielectric stack reliability of a high performance bulk planar 20nm replacement gate high-k metal gate technology and comparison to 28nm gate first high-k metal gate process
- W. McMahon
- C. Tian
- et al.
- 2013
- IRPS 2013
High performance bulk planar 20nm CMOS technology for low power mobile applications
- Huiling Shang
- Sameer Jain
- et al.
- 2012
- VLSI Technology 2012
A novel low resistance gate fill for extreme gate length scaling at 20nm and beyond for gate-last high-k/metal gate CMOS technology
- U. Kwon
- K. Wong
- et al.
- 2012
- VLSI Technology 2012
Performance elements for 28nm gate length bulk devices with gate first high-k metal gate
- Jun Yuan
- C. Gruensfelder
- et al.
- 2010
- ICSICT 2010