Analytical analysis of finite cache penalty and cycles per instruction of a multiprocessor memory hierarchy using miss rates and queuing theory
- Richard E. Matick
- Thomas J. Heller
- et al.
- 2001
- IBM J. Res. Dev
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16 results for Richard E. Matick
Modular nets (MNETS): A modular design methodology for computer timers
- R.E. Matick
- 1998
- IBM J. Res. Dev
Functional cache chip for improved system performance
- R.E. Matick
- 1989
- IBM J. Res. Dev
Architecture, design, and operating characteristics of a 12-ns CMOS functional cache chip
- R.E. Matick
- Robert Mao
- et al.
- 1989
- IBM J. Res. Dev
Comparison of Memory Chip Organizations vs Reliability in Virtual Memories
- Richard E. Matick
- 1983
- IEEE Transactions on Reliability
Transmission Line Pulse Transformers—Theory and Applications
- Richard E. Matick
- 1968
- Proceedings of the IEEE