3D copper TSV integration, testing and reliability
- Mukta Farooq
- T. Graves-Abe
- et al.
- 2011
- IEDM 2011
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9 results for Robert Hannon
Chip package interaction evaluation for a high performance 65nm and 45nm CMOS technology in a stacked die package with C4 and wirebond interconnections
- Christopher Muzzy
- David Danovitch
- et al.
- 2008
- ECTC 2008
A 45 nm CMOS node Cu/low-k/ ULtra low-k PECVD SiCOH (k=2.4) BEOL technology
- S. Sankaran
- S. Arai
- et al.
- 2006
- IEDM 2006
1GHz fully pipelined 3.7ns Address access time 8kx1024 embedded DRAM macro
- O. Takahashi
- S. Dhong
- et al.
- 2000
- ISSCC 2000
Copper through silicon via (TSV) for 3D integration
- C. Kothandaraman
- B. Himmel
- et al.
- 2012
- IRPS 2012
Process-design considerations for three dimensional memory integration
- S.S. Iyer
- T. Kirihata
- et al.
- 2009
- VLSI Technology 2009
65nm Cu integration and interconnect reliability in low stress K=2.75 SiCOH
- V. McGahay
- G. Bonilla
- et al.
- 2006
- IITC 2006
Spatial and temporal thermal characterization of stacked multicore architectures
- Eren Kursun
- Jamil Wakil
- et al.
- 2012
- ACM JETC
1-GHz fully pipelined 3.7-ns address access time 8 k × 1024 embedded synchronous DRAM macro
- Osamu Takahashi
- Sang H. Dhong
- et al.
- 2000
- IEEE Journal of Solid-State Circuits