A 500MHz random cycle 1.5ns-latency, SOI embedded DRAM macro featuring a 3T micro sense amplifier
- John Barth
- William Reohr
- et al.
- 2007
- ISSCC 2007
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13 results for John Barth
A 0.127 μm2 high performance 65 nm SOI based embedded DRAM for on-processor applications
- G. Wang
- K. Cheng
- et al.
- 2006
- IEDM 2006
Floating-body concerns for SOI dynamic random access memory (DRAM)
- J.A. Mandelman
- J. Barth
- et al.
- 1996
- IEEE International SOI Conference 1996