Nanoscale CMOS Circuit Leakage Power Reduction by Double-Gate Device
- Keunwoo Kim
- Koushik K. Das
- et al.
- 2004
- ISLPED 2004
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20 results for K. Das
Nanoscale CMOS circuit leakage power reduction By Double-gate device
- Keunwoo Kim
- Koushik K. Das
- et al.
- 2004
- ISLPED 2004
New optimal design strategies and analysis of ultra-low leakage circuits for nano-scale SOI technology
- K. Das
- R.V. Joshi
- et al.
- 2003
- ISLPED 2003
New Optimal Design Strategies and Analysis of Ultra-Low Leakage Circuits for Nano-Scale SOI Technology
- Koushik K. Das
- Rajiv V. Joshi
- et al.
- 2003
- ISLPED 2003
Reducing parasitic BJT effects in partially depleted SOI digital logic circuits
- Koushik K. Das
- Ching-Te Chuang
- et al.
- 2008
- Microelectronics Journal
High-density data-retention power gating structure using a four-terminal double-gate device
- K. Kim
- K. Das
- et al.
- 2007
- International Journal of Electronics
An integrated CAD methodology for evaluating MOSFET and parasitic extraction models and variability
- K. Koushik Das
- Steven G. Walker
- et al.
- 2007
- Proceedings of the IEEE
Ultralow-voltage minimum-energy CMOS
- Scott Hanson
- Bo Zhai
- et al.
- 2006
- IBM J. Res. Dev
Ring oscillators for CMOS process tuning and variability control
- Manjul Bhushan
- Anne Gattiker
- et al.
- 2006
- IEEE Trans Semicond Manuf
Leakage power analysis of 25-nm double-gate CMOS devices and circuits
- Keunwoo Kim
- Koushik K. Das
- et al.
- 2005
- IEEE Transactions on Electron Devices