Technology scaling effects on the ESD performance of silicide-blocked PMOSFET devices in nanometer bulk CMOS technologies
- Junjun Li
- Rahul Mishra
- et al.
- 2011
- EOS/ESD 2011
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4 results for Yang Yang
Pulsed gate dielectric breakdown in a 32 nm technology under different ESD stress configurations
- Yang Yang
- Robert Gauthier
- et al.
- 2010
- EOS/ESD 2010
Characterization of high-k/metal gate stack breakdown in the time scale of ESD events
- Yang Yang
- James Di Sarro
- et al.
- 2010
- IRPS 2010
Degradation of high-κ/metal gate nMOSFETs under ESD-like stress in a 32-nm technology
- Yang Yang
- Robert J. Gauthier
- et al.
- 2011
- IEEE T-DMR