Technology scaling effects on the ESD performance of silicide-blocked PMOSFET devices in nanometer bulk CMOS technologies
- Junjun Li
- Rahul Mishra
- et al.
- 2011
- EOS/ESD 2011
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5 results for Christian Russ
Technology scaling of advanced bulk CMOS on-chip ESD protection down to the 32nm node
- Junjun Li
- Kiran Chatty
- et al.
- 2009
- EOS/ESD 2009
ESD time-domain characterization of high-k gate dielectric in a 32 nm CMOS technology
- James Di Sarro
- Yang Yang
- et al.
- 2009
- EOS/ESD 2009
Analysis of failure mechanism on gate-silicided and gate-non-silicided, drain/source silicide-blocked ESD NMOSFETs in a 65nm bulk CMOS technology
- Junjun Li
- David Alvarez
- et al.
- 2006
- IPFA 2006
PMOSFET-based ESD protection in 65nm bulk CMOS technology for improved external latchup robustness
- Junjun Li
- Robert Gauthier
- et al.
- 2005
- EOS/ESD 2005