Full metal gate with borderless contact for 14 nm and beyond
- Soon-Cheon Seo
- L.F. Edge
- et al.
- 2011
- VLSI Technology 2011
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Gate capacitance reduction due to the inversion layer in high-k/metal gate stacks within a subnanometer EOT regime
- Ryosuke Iijima
- Lisa F. Edge
- et al.
- 2011
- IEEE T-ED