Analysis of failure mechanism on gate-silicided and gate-non-silicided, drain/source silicide-blocked ESD NMOSFETs in a 65nm bulk CMOS technology
- Junjun Li
- David Alvarez
- et al.
- 2006
- IPFA 2006
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19 results for Kiran Chatty
PMOSFET-based ESD protection in 65nm bulk CMOS technology for improved external latchup robustness
- Junjun Li
- Robert Gauthier
- et al.
- 2005
- EOS/ESD 2005
Model-based guidelines to suppress cable discharge event (CDE) induced latchup in CMOS ICs
- K. Chatty
- P.E. Cottrell
- et al.
- 2004
- IRPS 2004
Model-based guidelines to suppress cable discharge event (CDE) induced latchup in CMOS ICs
- K. Chatty
- P.E. Cottrell
- et al.
- 2004
- IRPS 2004
Optical and Electrical Testing of Latchup in I/O Interface Circuits
- Franco Stellari
- Peilin Song
- et al.
- 2003
- IEEE ITC 2003
Study of Critical Factors Determining Latchup Sensitivity of ICs using Emission Microscopy
- Franco Stellari
- Peilin Song
- et al.
- 2003
- ISTFA 2003
Latchup Analysis Using Emission Microscopy
- Franco Stellari
- Peilin Song
- et al.
- 2003
- Microelectronics Reliability
Degradation of high-κ/metal gate nMOSFETs under ESD-like stress in a 32-nm technology
- Yang Yang
- Robert J. Gauthier
- et al.
- 2011
- IEEE T-DMR
I/O interface latchup analysis using optical and electrical testing
- Franco Stellari
- Peilin Song
- et al.
- 2004
- Electronic Device Failure Analysis