A 1.8 pJ/bit 16 × 16Gb/s source-synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration
- Timothy O. Dickson
- Yong Liu
- et al.
- 2016
- IEEE JSSC
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23 results for Daniel Friedman
A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology
- Timothy O. Dickson
- Yong Liu
- et al.
- 2015
- IEEE JSSC
A 2.57mW 5.9-8.4GHz Cryogenic FinFET LNA for Qubit Readout
- Jean-Olivier Plouchart
- Dereje Yilma
- et al.
- 2022
- RFIC 2022
A Cryo-CMOS Transmon Qubit Controller and Verification with FPGA Emulation
- Kevin Tien
- Ken Inoue
- et al.
- 2022
- DATE 2022
Scaling Millimeter-Wave Phased Arrays: Challenges and Solutions
- Alberto Valdes-Garcia
- Bodhisatwa Sadhu
- et al.
- 2018
- BCICTS 2018
A gradient descent bias optimizer for oscillator phase noise reduction demonstrated in 45nm and 32nm SOI CMOS
- Mark Ferriss
- Bodhisatwa Sadhu
- et al.
- 2018
- RFIC 2018
Very low voltage (VLV) design
- Ramon Bertran
- Pradip Bose
- et al.
- 2017
- ICCD 2017
A 60GHz packaged switched beam 32nm CMOS TRX with broad spatial coverage, 17.1dBm peak EIRP, 6.1dB NF at < 250mW
- Bodhisatwa Sadhu
- Alberto Valdes-Garcia
- et al.
- 2016
- RFIC 2016
A 18mW, 3.3dB NF, 60GHz LNA in 32nm SOI CMOS technology with autonomic NF calibration
- Jean-Olivier Plouchart
- Fa Wang
- et al.
- 2015
- RFIC 2015
A capacitance boosted full-octave LC VCO based 0.7 to 24 GHz fractional-N synthesizer
- Bodhisatwa Sadhu
- Mark Ferriss
- et al.
- 2015
- RFIC 2015