A high performance 0.15 μm CMOS
- G. Shahidi
- J. Warnock
- et al.
- 1993
- VLSI Technology 1993
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50 results for B. Davari
Understanding of enhanced sensitivity to Hot Carrier degradation in drain engineered n-FETs
- C.C.-H. Hsu
- B.S. Wu
- et al.
- 1992
- SSDM 1992
Shallow junctions, silicide requirements and process technologies for sub 0.5 μm CMOS
- Bijan Davari
- 1992
- ESSDERC 1992
A high performance BiCMOS technology using 0.25 μm CMOS and double poly 47 GHz bipolar
- G. Shahidi
- J. Warnock
- et al.
- 1992
- VLSI Technology 1992
New preamorphization technique for very shallow p+-n junctions
- B. Davari
- E. Ganin
- et al.
- 1989
- VLSI Technology 1989
Workload and network-optimized computing systems
- D.P. LaPotin
- Shahrokh Daijavad
- et al.
- 2010
- IBM J. Res. Dev
1-GHz fully pipelined 3.7-ns address access time 8 k × 1024 embedded synchronous DRAM macro
- Osamu Takahashi
- Sang H. Dhong
- et al.
- 2000
- IEEE Journal of Solid-State Circuits
CMOS Scaling for High Performance and Low Power—The Next Ten Years
- Bijan Davari
- Robert H. Dennard
- et al.
- 1995
- Proceedings of the IEEE
CMOS scaling in the 0.1-μm, 1.X-volt regime for high-performance applications
- G. Shahidi
- J. Warnock
- et al.
- 1995
- IBM J. Res. Dev
A Room Temperature 0.1 µm CMOS on SOI
- Ghavam G. Shahidi
- Carl A. Anderson
- et al.
- 1994
- IEEE Transactions on Electron Devices