Practical strategies for power-efficient computing technologies
- Leland Chang
- David J. Frank
- et al.
- 2010
- Proceedings of the IEEE
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40 results for Paul Coteus
A 5.4mW 0.0035mm2 0.48psrms-jitter 0.8-to-5GHz non-PLL/DLL all-digital phase generator/rotator in 45nm SOI CMOS
- Kyu-Hyoun Kim
- Daniel M. Dreps
- et al.
- 2009
- ISSCC 2009
A 2.6mW 370MHz-to-2.5GHz open-loop quadrature clock generator
- Kyu-Hyoun Kim
- Paul W. Coteus
- et al.
- 2008
- ISSCC 2008
Overview of the IBM Blue Gene/P project
- Gheorghe Almasi
- Sameh Asaad
- et al.
- 2008
- IBM J. Res. Dev
The blue gene/L supercomputer: A hardware and software story
- José E. Moreira
- Valentina Salapura
- et al.
- 2007
- Int. J. Parallel Program
An 8 Gb/s/pin 9.6 ns row-cycle 288 Mb deca-data rate SDRAM with an I/O error detection scheme
- Kyu-Hyoun Kim
- Hoe-Ju Chung
- et al.
- 2007
- IEEE Journal of Solid-State Circuits
A holistic approach to system reliability in blue gene
- M. Blumrich
- D. Chen
- et al.
- 2006
- IWIA 2006
Power and performance optimization at the system level
- Valentina Salapura
- Randy Bickford
- et al.
- 2005
- CF 2005
Overview of the Blue Gene/L system architecture
- Alan Gara
- Matthias A. Blumrich
- et al.
- 2005
- IBM J. Res. Dev
Packaging the Blue Gene/L supercomputer
- Paul Coteus
- H. Randall Bickford
- et al.
- 2005
- IBM J. Res. Dev