A Best Balance Ratio Ordered Feature Selection Methodology for Robust and Fast Statistical Analysis of Memory Designs
- Lama Shaer
- Rouwaida Kanj
- et al.
- 2021
- IEEE TCADIS
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57 results at IEEE TCADIS
Group LARS based Iterative Reweighted Least Squares Methodology for Efficient Statistical Modeling of Memory Designs
- Lama Shaer
- Rouwaida Kanj
- et al.
- 2021
- IEEE TCADIS
Predictive Guardbanding: Program-Driven Timing Margin Reduction for GPUs
- Jingwen Leng
- Alper Buyuktosunoglu
- et al.
- 2021
- IEEE TCADIS
Temperature Aware Adaptations for Improved Read Reliability in STT-MRAM Memory Subsystem
- Saravanan Sethuraman
- Venkata Kalyan Tavva
- et al.
- 2020
- IEEE TCADIS
Optimized Selection of Reliable and Cost-Effective Safety-Critical System Architectures
- Pierluigi Nuzzo
- Nikunj Bajaj
- et al.
- 2020
- IEEE TCADIS
OWARU: Free space-aware timing-driven incremental placement with critical path smoothing
- Jinwook Jung
- Gi Joon Nam
- et al.
- 2018
- IEEE TCADIS
Machine Learning for Noise Sensor Placement and Full-Chip Voltage Emergency Detection
- Xiaochen Liu
- Shupeng Sun
- et al.
- 2017
- IEEE TCADIS
On the Optimal Threshold Voltage Computation of On-Chip Noise Sensors
- Tao Wang
- Chun Zhang
- et al.
- 2016
- IEEE TCADIS
Polynomial Time Algorithm for Area and Power Efficient Adder Synthesis in High-Performance Designs
- Subhendu Roy
- Mihir Choudhury
- et al.
- 2016
- IEEE TCADIS
TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip
- Filipp Akopyan
- Jun Sawada
- et al.
- 2015
- IEEE TCADIS