An overview of through-silicon-via technology and manufacturing challenges
- Jeffrey P. Gambino
- Shawn A. Adderly
- et al.
- 2015
- Microelectronic Engineering
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Lab-on-a-chip devices: How to close and plug the lab?
- Yuksel Temiz
- Robert D. Lovchik
- et al.
- 2015
- Microelectronic Engineering
Resistless nanofabrication by stencil lithography: A review
- O. Vazquez-Mena
- Leo Gross
- et al.
- 2015
- Microelectronic Engineering
Challenges of nickel silicidation in CMOS technologies
- Nicolas Breil
- Christian Lavoie
- et al.
- 2015
- Microelectronic Engineering
Dependence of Cu electromigration resistance on selectively deposited CVD Co cap thickness
- C.-C. Yang
- F. Baumann
- et al.
- 2013
- Microelectronic Engineering
Evolution of stress gradients in Cu films and features induced by capping layers
- Conal E. Murray
- E.T. Ryan
- et al.
- 2012
- Microelectronic Engineering
Competitive and cost effective copper/low-k interconnect (BEOL) for 28 nm CMOS technologies
- R. Augur
- C. Child
- et al.
- 2012
- Microelectronic Engineering
Processing and moisture effects on TDDB for Cu/ULK BEOL structures
- E. Liniger
- T.M. Shaw
- et al.
- 2012
- Microelectronic Engineering
Co capping layers for Cu/low-k interconnects
- C.-C. Yang
- P. Flaitz
- et al.
- 2012
- Microelectronic Engineering
Synergistic combinations of dielectrics and metallization process technology to achieve 22 nm interconnect performance targets
- G.A. Antonelli
- G. Jiang
- et al.
- 2012
- Microelectronic Engineering