Effective Cu surface pre-treatment for high-reliable 22 nm-node Cu dual damascene interconnects with high plasma resistant ultra low-k dielectric (k = 2.2)
- F. Ito
- H. Shobha
- et al.
- 2012
- Microelectronic Engineering
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Synergistic combinations of dielectrics and metallization process technology to achieve 22 nm interconnect performance targets
- G.A. Antonelli
- G. Jiang
- et al.
- 2012
- Microelectronic Engineering
Effects of chemical mechanical polishing on a porous SiCOH dielectric
- S. Gates
- S. Papa Rao
- et al.
- 2012
- Microelectronic Engineering
1.2 nm capacitance equivalent thickness gate stacks on Si-passivated GaAs
- M. El Kazzi
- D.J. Webb
- et al.
- 2011
- Microelectronic Engineering
Epitaxial strontium oxide layers on silicon for gate-first and gate-last TiN/HfO2 gate stack scaling
- Martin M. Frank
- Chiara Marchiori
- et al.
- 2011
- Microelectronic Engineering
Phase formation and texture of nickel silicides on Si1-xC x epilayers
- K. De Keyser
- B. De Schutter
- et al.
- 2011
- Microelectronic Engineering
New opportunities for SiGe and Ge channel p-FETs
- S.W. Bedell
- N. Daval
- et al.
- 2011
- Microelectronic Engineering
3D opto-electrical device stacking on CMOS
- L. Dellmann
- Ute Drechsler
- et al.
- 2010
- Microelectronic Engineering
In situ X-ray diffraction study of thin film Ir/Si solid state reactions
- W. Knaepen
- J. Demeulemeester
- et al.
- 2010
- Microelectronic Engineering
In situ study of the formation of silicide phases in amorphous Co-Si mixed layers
- C. Van Bockstael
- K. De Keyser
- et al.
- 2010
- Microelectronic Engineering