CMOS scaling in the 0.1-μm, 1.X-volt regime for high-performance applications
- G. Shahidi
- J. Warnock
- et al.
- 1995
- IBM J. Res. Dev
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Architectural timing verification of CMOS RISC processors
- Pradip Bose
- S. Surya
- 1995
- IBM J. Res. Dev
Electromigration and stress-induced voiding in fine Al and Al-alloy thin-film lines
- C.-K. Hu
- K.P. Rodbell
- et al.
- 1995
- IBM J. Res. Dev
CMOS circuits for Gb/s serial data communication
- J.F. Ewen
- M. Soyuer
- et al.
- 1995
- IBM J. Res. Dev
Low-noise TTL-compatible CMOS off-chip driver circuit
- S. Dhong
- M. Tanaka
- et al.
- 1995
- IBM J. Res. Dev
Verity - a formal verification program for custom CMOS circuits
- Andreas Kuehlmann
- A. Srinivasan
- et al.
- 1995
- IBM J. Res. Dev
High-level synthesis in an industrial environment
- Reinaldo A. Bergamaschi
- R.A. O'Connor
- et al.
- 1995
- IBM J. Res. Dev
Performance of fiber-optic data links using 670-nm cw VCSELs and a monolithic Si photodetector and CMOS preamplifier
- D. Kuchta
- H. Ainspan
- et al.
- 1995
- IBM J. Res. Dev
CMOS scaling into the 21st century: 0.1 μm and beyond
- Y. Taur
- Y. Mii
- et al.
- 1995
- IBM J. Res. Dev
Component procurement and allocation for products assembled to forecast: Risk-pooling effects
- Stephen J. Grotzinger
- R. Srinivasan
- et al.
- 1993
- IBM J. Res. Dev