A DPLL-based per core variable frequency clock generator for an eight-core POWER7™ microprocessor
- Jose Tierno
- Alexander Rylyakov
- et al.
- 2010
- VLSI Circuits 2010
Publications
3 results at VLSI Circuits 2010
A compact 6 GHz to 12 GHz digital PLL with coupled dual-LC tank DCO
- A. Goel
- Alexander V. Rylyakov
- et al.
- 2010
- VLSI Circuits 2010
A fully-integrated switched-capacitor 2:1 Voltage converter with regulation capability and 90% efficiency at 2.3A/mm2
- Leland Chang
- Robert K. Montoye
- et al.
- 2010
- VLSI Circuits 2010