Technology scaling of advanced bulk CMOS on-chip ESD protection down to the 32nm nodeJunjun LiKiran Chattyet al.2009EOS/ESD 2009
A thermodynamic study of ESD and EOS induced pinned layer reversal in GMR sensorsIcko Eric Timothy Iben2009EOS/ESD 2009
ESD time-domain characterization of high-k gate dielectric in a 32 nm CMOS technologyJames Di SarroYang Yanget al.2009EOS/ESD 2009
A study of ESD protection means of cabled GMR sensorsMichelle LamIcko Eric Timothy Ibenet al.2009EOS/ESD 2009