1GHz fully pipelined 3.7ns Address access time 8kx1024 embedded DRAM macro
- O. Takahashi
- S. Dhong
- et al.
- 2000
- ISSCC 2000
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8 results at ISSCC 2000
Asynchronous interlocked pipelined CMOS circuits operating at 3.3-4.5Ghz
- S.E. Schuster
- W. Reohr
- et al.
- 2000
- ISSCC 2000
Non-invasive timing analysis of IBM G6 microprocessor L1 cache using backside time-resolved hot electron luminescence
- S. Polonsky
- D.R. Knebel
- et al.
- 2000
- ISSCC 2000
Delay variability: Sources, impacts and trends
- S. Nassif
- 2000
- ISSCC 2000
SiGe BICMOS 3.3V clock and data recovery circuits for 10Gb/s serial transmission systems
- M. Meghelli
- B. Parker
- et al.
- 2000
- ISSCC 2000
A 10ns read and write non-volatile memory array using a magnetic tunnel junction and FET switch in each cell
- R. Scheuerlein
- W.J. Gallagher
- et al.
- 2000
- ISSCC 2000
A 1GHz single-issue 64b powerPC processor
- H.P. Hofstee
- Naoaki Aoki
- et al.
- 2000
- ISSCC 2000
Millipede - A highly-parallel dense scanning-probe-based data-storage system
- M.I. Lutwyche
- G. Cross
- et al.
- 2000
- ISSCC 2000