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A 50GB/S 1.6PJ/B RX Data-Path with Quarter-Rate 3-Tap Speculative DFEPier Andrea FranceseAlessandro Cevreroet al.2018VLSI Circuits 2018
A Scalable Multi-TeraOPS Deep Learning Processor Core for AI Trainina and InferenceBruce FleischerSunil Shuklaet al.2018VLSI Circuits 2018
A 10-Bit 20-40 GS/S ADC with 37 dB SNDR at 40 GHz Input Using First Order Sampling Bandwidth CalibrationLukas KullDanny Luuet al.2018VLSI Circuits 2018