A 1.8-pJ/bit 16x16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration
- Timothy O. Dickson
- Yong Liu
- et al.
- 2015
- CICC 2015
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5 results at CICC 2015
Non-resistance metric based read scheme for multi-level PCRAM in 25 nm technology
- Junho Cheon
- Insoo Lee
- et al.
- 2015
- CICC 2015
Symmetry breaking in the drain current of multi-finger transistors
- Ning Lu
- Sungjae Lee
- et al.
- 2015
- CICC 2015
A fully-functional 90nm 8Mb STT MRAM demonstrator featuring trimmed, reference cell-based sensing
- J. DeBrosse
- T. Maffitt
- et al.
- 2015
- CICC 2015
Materials challenges for III-V/Si co-integrated CMOS
- Devendra Sadana
- Cheng-Wei Cheng
- et al.
- 2015
- CICC 2015