A 6-bit drift-resilient readout scheme for multi-level phase-change memory
- A. Athmanathan
- Milos Stanisavljevic
- et al.
- 2014
- A-SSCC 2014
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2 results at A-SSCC 2014
A 110 mW 6 bit 36 GS/s interleaved SAR ADC for 100 GBE occupying 0.048 mm2 in 32 nm SOI CMOS
- Lukas Kull
- J. Pliva
- et al.
- 2014
- A-SSCC 2014