I received my graduation degree from Fergusson College, University of Pune, India in 1995, where my thesis work focussed on design of self calibrating pH and conductivity meters.
From 1995 to 1996, I received a Defense Research Development Organisation Scholarship to model hot-carrier injection in MOSFETS at the Department of Electronic Science, University of Pune.
In the spring of 1996, I joined the memory products group at ST Microelctronics, where I worked on the design and development of SRAMs in the 0.5 micron technology.
In the summer of 1997, I joined the IBM Global Services division, working on the design of eDRAM cells for the 180nm technology.
In the spring of 1998, I joined the T. J. Watson Research lab, IBM where I have had the priviledge to work on the world's first 2M pixel CMOS array for digital cameras, read channel circuits for disk drives, fractional-n-synthesizers for cell phones, package models for signal integrity analysis, adaptive feedback circuits for high speed serial links, world's first large scale FPGA based emulator for the Blue Gene supercomputer chips, design and development of novel processor architecture for hardware based malware defense, room temperature control electronics for world's first 20 QuBit Quantum Computer.
My current interests lie in the space of cloud security, direct digital synthesis of control signals for a transmon QuBit, hardware accelerators for genome mapping and variant detection.