Phillip J Restle           

Phillip J. Restle received a B.A. in Physics from Oberlin College in 1979, and a Ph.D. in physics from the University of Illinois at Urbana in 1986. He then joined the IBM T. J. Watson Research Center, where he is a Distinguished Research Staff Member.

Phillip Restle is a recognized leader in high performance global clock distribution.  The continually evolving strategies, methodology, and design tools he developed have been a key differentiator used on all IBM P and Z servers for the past 20 years.  Phillip also led the research and realization of resonant clocking, recently implemented across the entire IBM P and Z product lines, resulting in a significant boost in power/performance boost for all POWER and zSeries systems beginning with 22nm designs.  Resonant clocking saves power by recycling energy using over 1000 on-chip inductors. More recently, he is involved in the design and test of power supply noise mitigation strategies (presented at ISSCC'2017). 

Dr. Restle received three IBM corporate awards related to high performance clocking methodology, and. He received a 2005 Pat Goldberg Memorial Best Paper award and 2007 ITC best paper award. Restle has published over 63 papers, (including 14 ISSCC conference papers, and 11 JSSC papers), 34 patents, and has been invited to preset at tutorials, forums, and plenary talks on clock distribution, high frequency on-chip interconnects, and technical visualizations in VLSI design.  

Professional Activities

Serves on the IEEE ISSCC'2018 (International Solid State Circuits Conference) DCT (Digital Circuits) Subcommittee

Served as the co-chair of the 2013 Silicon Research Corporation Summer Study on Advanced Interconnects

Interests

Microprocessor clocking, clock distribution networks, on-chip inductance, passive and adaptive noise-mitigation strategies, interconnect optimization, VLSI design, CAD tools/Design Automation, technical visualization, and 3D design.