Hasan M Nayfeh  Hasan M Nayfeh photo         

contact information

Senior Research and Development Engineer, Quantum Computing
Thomas J. Watson Research Center, Yorktown Heights, NY USA


Professional Associations

Professional Associations:  IEEE Electron Devices Society (EDS)


Demonstration of quantum volume 64 on a superconducting quantum computing system
Petar Jurcevic, Ali Javadi-Abhari, Lev S. Bishop, Isaac Lauer, Daniela F. Bogorin, Markus Brink, Lauren Capelluto, Oktay Gunluk, Toshinari Itoko, Naoki Kanazawa, Abhinav Kandala, George A. Keefe, Kevin Krsulich, William Landers, Eric P. Lewandowski, Douglas T. McClure, Giacomo Nannicini, Adinath Narasgond, Hasan M. Nayfeh, Emily Pritchett, Mary Beth Rothwell, Srikanth Srinivasan, Neereja Sundaresan, Cindy Wang, Ken X. Wei, Christopher J. Wood, Jeng-Bang Yau, Eric J. Zhang, Oliver E. Dial, Jerry M. Chow, Jay
arXiv.org, 2020


A 7nm CMOS technology platform for mobile and high performance compute application
S. Narasimha, B. Jagannathan, A. Ogino, D. Jaeger, B. Greene, C. Sheraw, K. Zhao, B. Haran, U. Kwon, A. K. M. Mahalingam, B. Kannan, B. Morganfeld, J. Dechene, C. Radens, A. Tessier, A. Hassan, H. Narisetty, I. Ahsan, M. Aminpur, C. An, M. Aquilino, A. Arya, R. Augur, N. Baliga, R. Bhelkar, G. Biery, A. Blauberg, N. Borjemscaia, A. Bryant, L. Cao, V. Chauhan, M. Chen, L. Cheng, J. Choo, C. Christiansen, T. Chu, B. Cohen, R. Coleman, D. Conklin, S. Crown, A. da Silva, D. Dechene, G. Derderian, S. Deshpande,
2017 IEEE International Electron Devices Meeting (IEDM)
Abstract   static random access memory, physics, low voltage, logic gate, immersion lithography, extreme ultraviolet lithography, electronic engineering, capacitance, cmos, architecture


SOI FinFET nFET-to-pFET Tracking Variability Compact Modeling and Impact on Latch Timing
Jie Deng, Ardasheir Rahman, Rainer Thoma, Peter W. Schneider, Jim Johnson, Henry Trombley, Ning Lu, Richard Q. Williams, Hasan M. Nayfeh, Kai Zhao, Russ Robison, Ximeng Guan, Noah Zamdmer, Steve Shuma, Brian Worth, James E. Sundquist, Eric A. Foreman, Scott K. Springer, Rick Wachnik
IEEE Transactions on Electron Devices 62(6), 1760-1768, 2015
Abstract   work function, threshold voltage, silicon on insulator, physics, monte carlo method, metal gate, logic gate, electronic engineering, electronic circuit, cmos


High performance 14nm SOI FinFET CMOS technology with 0.0174ÿýÿm 2 embedded DRAM and 15 levels of Cu metallization
C-H. Lin, B. Greene, S. Narasimha, J. Cai, A. Bryant, C. Radens, V. Narayanan, B. Linder, H. Ho, A. Aiyar, E. Alptekin, J-J. An, M. Aquilino, R. Bao, V. Basker, N. Breil, M. Brodsky, W. Chang, L. Clevenger, D. Chidambarrao, C. Christiansen, D. Conklin, C. DeWan, H. Dong, L. Economikos, B. Engel, S. Fang, D. Ferrer, A. Friedman, A. Gabor, F. Guarin, X. Guan, M. Hasanuzzaman, J. Hong, D. Hoyos, B. Jagannathan, S. Jain, S-J. Jeng, J. Johnson, B. Kannan, Y. Ke, B. Khan, B. Kim, S. Koswatta, A. Kumar, T. Kwon, U
IEDM, International Electron Devices Meeting, 2014


Trade-Offs Between RF Performance and Total-Dose Tolerance in 45-nm RF-CMOS
R. Arora, En Xia Zhang, S. Seth, J. D. Cressler, D. M. Fleetwood, R. D. Schrimpf, G. L. Rosa, A. K. Sutton, H. M. Nayfeh, G. Freeman
IEEE Transactions on Nuclear Science 58(6), 2830-2837, 2011
Abstract   silicon on insulator, radio frequency, radiation, physics, optoelectronics, mosfet, logic gate, impact ionization, electronic engineering, doping, cmos

Impact of Source/Drain contact and gate finger spacing on the RF reliability of 45-nm RF nMOSFETs
Rajan Arora, Sachin Seth, John Chung Hang Poh, John D. Cressler, Akil K. Sutton, Hasan M. Nayfeh, Giuseppe L. Rosa, Greg Freeman
2011 International Reliability Physics Symposium
Abstract   silicon on insulator, radio frequency, mosfet, logic gate, leakage, gate oxide, engineering, electronic engineering, electrical engineering, and gate


Investigation of kink-induced excess RF channel noise in sub -50 nm PD-SOI MOSFETs
Ninad S. Wadje, Vijaya Bhaskara Neeli, R. P. Jindal, H. M. Nayfeh, R. Todi
2010 IEEE International SOI Conference (SOI), pp. 1-2
Abstract   velocity saturation, silicon on insulator, mosfet, impact ionization, floating body effect, engineering, electronic engineering, electrical engineering, conductance, channel, channel length modulation

Evaluating the Influence of Various Body-Contacting Schemes on Single Event Transients in 45-nm SOI CMOS
K A Moen, S D Phillips, E P Wilcox, J D Cressler, H Nayfeh, A K Sutton, J H Warner, S P Buchner, D McMorrow, G Vizkelethy, P Dodd
IEEE Transactions on Nuclear Science 57(6), 3366-3372, 2010
Abstract   silicon on insulator, pulsed laser deposition, physics, optoelectronics, mosfet, laser, electronics, electronic engineering, cmos

Impact of body tie and Source/Drain contact spacing on the hot carrier reliability of 45-nm RF-CMOS
Rajan Arora, Kurt A. Moen, Anuj Madan, John D. Cressler, Enxia Zhang, Daniel M. Fleetwood, Ronald D. Schrimpf, Akil K. Sutton, Hasan M. Nayfeh
2010 IEEE International Integrated Reliability Workshop Final Report, pp. 56-60
Abstract   silicon on insulator, radio frequency, radiation, electronic engineering, electric field, doping, computer science, cmos


Impact of lateral asymmetric channel doping on 45-nm-technology N-type SOI MOSFETs
Nayfeh, Hasan M and Rovedo, Nivo and Bryant, Andres and Narasimha, Shreesh and Kumar, Arvind and Yu, Xiaojun and Su, Ning and Sleight, Jeffrey W and Robison, Robert R and Rausch, Werner and others
IEEE Transactions on Electron Devices 56(12), 3097--3105, IEEE, 2009


Channel strain engineering for high performance CMOS technology
Hasan M. Nayfeh
2008 16th IEEE International Conference on Advanced Thermal Processing of Semiconductors
Abstract   thermal velocity, strain engineering, silicon on insulator, nanotechnology, materials science, electronic engineering, compressive strength, channel, cmos, analytical chemistry

Yield monitor for embedded-sige process optimization
Xu Ouyang, Shwu-Jen Jeng, I. Ahsan, A. Waite, K. Barth, H.M. Nayfeh, Yunyu Wang
2008 9th International Conference on Solid-State and Integrated-Circuit Technology, pp. 1142-1145
Abstract   transistor, static random access memory, process optimization, materials science, logic gate, leakage, integrated circuit layout, electronic engineering


Hole Transport in Nanoscale p-type MOSFET SOI Devices with High Strain
H.M. Nayfeh, S. Jeng, S. Narasimha, S. Butt, R. Pal, A. Waite, K. Tabakman, J.B. Johnson, J. Liu, J. Holt, T. Adam, A. Madan, A. Domenicucci
2007 65th Annual Device Research Conference, pp. 51-52
Abstract   strain engineering, strain, silicon on insulator, silicon nitride, physics, nanoelectronics, mosfet, electronic engineering, electron mobility, channel length modulation

(110) channel, SiON gate-dielectric PMOS with record high I on =1 mA/m through channel stress and source drain external resistance (R ext ) engineering
B. Yang, A. Waite, H. Yin, J. Yu, L. Black, D. Chidambarrao, A. Domenicucci, X. Wang, S.H. Ku, Y. Wang, H.V. Meer, B. Kim, H. Nayfeh, S.D. Kim, K. Tabakman, R. Pal, K. Nummy, B. Greene, P. Fisher, J. Liu, Q. Liang, J. Holt, S. Narasimha, Z. Luo, H. Utomo, X. Chen, D. Park, C. Sung, R. Wachnik, G. Freeman, D. Schepis, E. Maciejewski, M. Khare, E. Leobandung, S. Luning, P. Agnello
2007 IEEE International Electron Devices Meeting, pp. 1032-1034
Abstract   physics, pmos logic, optoelectronics, mosfet, ion, gate oxide, gate dielectric, electronic engineering, dielectric, degradation, channel


Effect of tensile uniaxial stress on the electron transport properties of deeply scaled FD-SOI n-type MOSFETs
Nayfeh, HM and Singh, DV and Hergenrother, JM and Sleight, JW and Ren, Z and Dokumaci, O and Black, L and Chidambarrao, D and Venigalla, R and Pan, J and others
IEEE electron device letters 27(4), 288--290, IEEE, 2006

High performance 45-nm SOI technology with enhanced strain, porous low-k BEOL, and immersion lithography
S Narasimha, K Onishi, HM Nayfeh, A Waite, M Weybright, J Johnson, C Fonseca, D Corliss, C Robinson, M Crouse, others
Electron Devices Meeting, 2006, pp. 1--4


Effect of contact liner stress in high-performance FDSOI devices with ultra-thin silicon channels and 30 nm gate lengths
Singh, DV and Hergenrother, JM and Sleight, JW and Ren, Z and Nayfeh, H and Dokumaci, O and Black, L and Chidambarrao, D and Venigalla, R and Pan, J and others
2005 IEEE International SOI Conference Proceedings, pp. 178--179


A physically based analytical model for the threshold voltage of strained-Si n-MOSFETs
H.M. Nayfeh, J.L. Hoyt, D.A. Antoniadis
IEEE Transactions on Electron Devices 51(12), 2069-2072, 2004
Abstract   threshold voltage, reverse short channel effect, physics, mosfet, heterojunction, gate oxide, extrinsic semiconductor, electronic engineering, doping, band gap

Advanced gate stacks with fully silicided (FUSI) gates and high-/spl kappa/ dielectrics: enhanced performance at reduced gate leakage
E.P. Gusev, C. Cabral, B.P. Under, Y.H. Kim, K. Maitra, H. Nayfeh, R. Amos, G. Biery, N. Bojarczuk, A. Callegari, R. Carruthers, S.A. Cohen, M. Copel, S. Fang, M. Frank, S. Guha, M. Gribelyuk, P. Jamison, R. Jammy, M. Ieong, J. Kedzierski, P. Kozlowski, K. Ku, D. Lacey, D. LaTulipe, V. Narayanan, H. Ng, P. Nguyen, J. Newbury, V. Paruchuri, R. Rengarajan, G. Shahidi, A. Steegen, M. Steen, S. Zafar, Y. Zhang
IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004., pp. 79-82
Abstract   threshold voltage, physics, nickel compounds, leakage, field effect transistor, electronic engineering, electron mobility, dielectric

Technical Areas